#ifndef _SDHCI_REG_H
#define _SDHCI_REG_H
#include "cv181x_reg.h"
#define REG_TOP_SD_PWRSW_CTRL (0x1F4)

#define REG_SDIO0_PAD_MASK (0xFFFFFFF3)
#define REG_SDIO0_PAD_SHIFT (2)

#define REG_SDIO0_PAD_CLR_MASK (0xC)
#define REG_SDIO0_CD_PAD_REG (PINMUX_BASE + 0x900)
#define REG_SDIO0_CD_PAD_VALUE (1)
#define REG_SDIO0_CD_PAD_RESET (1)

#define REG_SDIO0_PWR_EN_PAD_REG (PINMUX_BASE + 0x904)
#define REG_SDIO0_PWR_EN_PAD_VALUE (2)
#define REG_SDIO0_PWR_EN_PAD_RESET (2)

#define REG_SDIO0_CLK_PAD_REG (PINMUX_BASE + 0xA00)
#define REG_SDIO0_CLK_PAD_VALUE (2)
#define REG_SDIO0_CLK_PAD_RESET (2)

#define REG_SDIO0_CMD_PAD_REG (PINMUX_BASE + 0xA04)
#define REG_SDIO0_CMD_PAD_VALUE (1)
#define REG_SDIO0_CMD_PAD_RESET (2)

#define REG_SDIO0_DAT0_PAD_REG (PINMUX_BASE + 0xA08)
#define REG_SDIO0_DAT0_PAD_VALUE (1)
#define REG_SDIO0_DAT0_PAD_RESET (2)

#define REG_SDIO0_DAT1_PAD_REG (PINMUX_BASE + 0xA0C)
#define REG_SDIO0_DAT1_PAD_VALUE (1)
#define REG_SDIO0_DAT1_PAD_RESET (2)

#define REG_SDIO0_DAT2_PAD_REG (PINMUX_BASE + 0xA10)
#define REG_SDIO0_DAT2_PAD_VALUE (1)
#define REG_SDIO0_DAT2_PAD_RESET (2)

#define REG_SDIO0_DAT3_PAD_REG (PINMUX_BASE + 0xA14)
#define REG_SDIO0_DAT3_PAD_VALUE (1)
#define REG_SDIO0_DAT3_PAD_RESET (2)

#define PAD_SDIO0_CD_REG (PINMUX_BASE + 0x34)
#define PAD_SDIO0_PWR_EN_REG (PINMUX_BASE + 0x38)
#define PAD_SDIO0_CLK_REG (PINMUX_BASE + 0x1C)
#define PAD_SDIO0_CMD_REG (PINMUX_BASE + 0x20)
#define PAD_SDIO0_D0_REG (PINMUX_BASE + 0x24)
#define PAD_SDIO0_D1_REG (PINMUX_BASE + 0x28)
#define PAD_SDIO0_D2_REG (PINMUX_BASE + 0x2C)
#define PAD_SDIO0_D3_REG (PINMUX_BASE + 0x30)

#define REG_SDIO1_PAD_MASK (0xFFFFFFF3)
#define REG_SDIO1_PAD_SHIFT (2)

#define SDIO1_PAD_BASE 0x05027000
#define REG_SDIO1_PAD_CLR_MASK (0xC)
#define REG_SDIO1_CLK_PAD_REG (SDIO1_PAD_BASE + 0x06C)
#define REG_SDIO1_CLK_PAD_VALUE (2)

#define REG_SDIO1_CMD_PAD_REG (SDIO1_PAD_BASE + 0x068)
#define REG_SDIO1_CMD_PAD_VALUE (1)

#define REG_SDIO1_DAT0_PAD_REG (SDIO1_PAD_BASE + 0x064)
#define REG_SDIO1_DAT0_PAD_VALUE (1)

#define REG_SDIO1_DAT2_PAD_REG (SDIO1_PAD_BASE + 0x05C)
#define REG_SDIO1_DAT2_PAD_VALUE (1)

#define REG_SDIO1_DAT1_PAD_REG (SDIO1_PAD_BASE + 0x060)
#define REG_SDIO1_DAT1_PAD_VALUE (1)

#define REG_SDIO1_DAT3_PAD_REG (SDIO1_PAD_BASE + 0x058)
#define REG_SDIO1_DAT3_PAD_VALUE (1)

#define REG_EMMC_PAD_CLR_MASK (0xC)
#define REG_EMMC_PAD_SHIFT (2)

#define REG_EMMC_RSTN_PAD_REG (PINMUX_BASE + 0x914)
#define REG_EMMC_RSTN_PAD_VALUE (1)

#define REG_EMMC_CLK_PAD_REG (PINMUX_BASE + 0x91c)
#define REG_EMMC_CLK_PAD_VALUE (2)

#define REG_EMMC_CMD_PAD_REG (PINMUX_BASE + 0x928)
#define REG_EMMC_CMD_PAD_VALUE (1)

#define REG_EMMC_DAT0_PAD_REG (PINMUX_BASE + 0x920)
#define REG_EMMC_DAT0_PAD_VALUE (1)

#define REG_EMMC_DAT1_PAD_REG (PINMUX_BASE + 0x92C)
#define REG_EMMC_DAT1_PAD_VALUE (1)

#define REG_EMMC_DAT2_PAD_REG (PINMUX_BASE + 0x918)
#define REG_EMMC_DAT2_PAD_VALUE (1)

#define REG_EMMC_DAT3_PAD_REG (PINMUX_BASE + 0x924)
#define REG_EMMC_DAT3_PAD_VALUE (1)

#define CVI_SDHCI_VENDOR_OFFSET 0x200
#define CVI_SDHCI_PHY_TX_RX_DLY	(CVI_SDHCI_VENDOR_OFFSET + 0x40)
#define CVI_SDHCI_PHY_DS_DLY	(CVI_SDHCI_VENDOR_OFFSET + 0x44)
#define CVI_SDHCI_PHY_DLY_STS	(CVI_SDHCI_VENDOR_OFFSET + 0x48)
#define CVI_SDHCI_PHY_CONFIG	(CVI_SDHCI_VENDOR_OFFSET + 0x4C)

#define CVI_SDHCI_BIT_CLK_FREE_EN 2
#define CVI_SDHCI_CLK_FREE_EN_VALUE 0
#define CVI_SDHCI_CLK_FREE_EN_MASK 0xFFFFFFFB
#define CVI_SDHCI_VENDOR_MSHC_CTRL_R (CVI_SDHCI_VENDOR_OFFSET + 0x0)
#define CVI_SDHCI_PHY_RX_DLY_SHIFT 16
// Bit 16~22
#define CVI_SDHCI_PHY_RX_DLY_MASK 0x7F0000
#define CVI_SDHCI_PHY_TX_RX_DLY (CVI_SDHCI_VENDOR_OFFSET + 0x40)
#define CVI_SDHCI_PHY_RX_SRC_BIT_1 24
#define CVI_SDHCI_PHY_RX_SRC_BIT_2 25

#define SDHCI_PHY_CONFIG                                                       \
	(CVI_SDHCI_VENDOR_OFFSET +                                             \
	 0x4C) // P_VERDOR_SPECIFIC_AREA + 0x4c0x24c( PHY_TX_BPS )
#define REG_TX_BPS_SEL_MASK 0xFFFFFFFE
#define REG_TX_BPS_SEL_CLR_MASK (0x1) // 0x24c  PHY_TX_BPS
#define REG_TX_BPS_SEL_SHIFT (0) // 0x24c  PHY_TX_BPS
#define REG_TX_BPS_SEL_BYPASS (1) // 0x24c PHY_TX_BPS inv

#define MMC_MAX_CLOCK (375000000)
#define MMC_MAX_CLOCK_DIV_VALUE (0x40009)
#define CLOCK_BYPASS_SELECT_REGISTER (0x3002030)

#define MAX_TUNING_CMD_RETRY_COUNT 50
#define TUNE_MAX_PHCODE	128
#define TAP_WINDOW_THLD 20
#endif
